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dc.contributor.supervisor Rice, Jacqueline E.
dc.contributor.author Latif, Shamria Sabatina
dc.contributor.author University of Lethbridge. Faculty of Arts and Science
dc.date.accessioned 2018-08-23T16:32:14Z
dc.date.available 2018-08-23T16:32:14Z
dc.date.issued 2018
dc.identifier.uri https://hdl.handle.net/10133/5193
dc.description.abstract In recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy dissipation by eliminating the possibility of information loss. However, it is also desirable that all computation should ideally be done in a fault tolerant manner. To address this we propose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits. en_US
dc.language.iso en_US en_US
dc.publisher Lethbridge, Alta. : Universtiy of Lethbridge, Department of Mathematics and Computer Science en_US
dc.relation.ispartofseries Thesis (University of Lethbridge. Faculty of Arts and Science) en_US
dc.subject Reversible computing en_US
dc.subject Integrated circuits -- Fault tolerance en_US
dc.subject Logic circuits en_US
dc.subject majority voter circuit en_US
dc.subject passive hardware redundancy en_US
dc.subject reversible fault tolerant circuits en_US
dc.subject reversible logic en_US
dc.subject triple modular redundancy en_US
dc.subject zero energy dissipation en_US
dc.subject Dissertations, Academic en_US
dc.title Fault tolerance in reversible logic en_US
dc.type Thesis en_US
dc.publisher.faculty Arts and Science en_US
dc.publisher.department Department of Mathematics & Computer Science en_US
dc.degree.level Masters en_US
dc.proquest.subject 0984 en_US
dc.proquest.subject 0405 en_US
dc.proquest.subject 0544 en_US
dc.proquestyes Yes en_US
dc.embargo No en_US


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