Fault tolerance in reversible logic

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dc.contributor.authorLatif, Shamria Sabatina
dc.contributor.authorUniversity of Lethbridge. Faculty of Arts and Science
dc.contributor.supervisorRice, Jacqueline E.
dc.date.accessioned2018-08-23T16:32:14Z
dc.date.available2018-08-23T16:32:14Z
dc.date.issued2018
dc.degree.levelMastersen_US
dc.description.abstractIn recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy dissipation by eliminating the possibility of information loss. However, it is also desirable that all computation should ideally be done in a fault tolerant manner. To address this we propose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits.en_US
dc.embargoNoen_US
dc.identifier.urihttps://hdl.handle.net/10133/5193
dc.language.isoen_USen_US
dc.proquest.subject0984en_US
dc.proquest.subject0405en_US
dc.proquest.subject0544en_US
dc.proquestyesYesen_US
dc.publisherLethbridge, Alta. : Universtiy of Lethbridge, Department of Mathematics and Computer Scienceen_US
dc.publisher.departmentDepartment of Mathematics & Computer Scienceen_US
dc.publisher.facultyArts and Scienceen_US
dc.relation.ispartofseriesThesis (University of Lethbridge. Faculty of Arts and Science)en_US
dc.subjectReversible computingen_US
dc.subjectIntegrated circuits -- Fault toleranceen_US
dc.subjectLogic circuitsen_US
dc.subjectmajority voter circuiten_US
dc.subjectpassive hardware redundancyen_US
dc.subjectreversible fault tolerant circuitsen_US
dc.subjectreversible logicen_US
dc.subjecttriple modular redundancyen_US
dc.subjectzero energy dissipationen_US
dc.subjectDissertations, Academicen_US
dc.titleFault tolerance in reversible logicen_US
dc.typeThesisen_US
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