Synthesis, testing and tolerance in reversible logic

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dc.contributor.authorNashiry, Md Asif
dc.contributor.authorUniversity of Lethbridge. Faculty of Arts and Science
dc.contributor.supervisorRice, Jacqueline E.
dc.date.accessioned2018-01-24T16:01:07Z
dc.date.available2018-01-24T16:01:07Z
dc.date.issued2017
dc.degree.levelPh.Den_US
dc.description.abstractIn recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits.en_US
dc.embargoNoen_US
dc.identifier.urihttps://hdl.handle.net/10133/5022
dc.language.isoen_USen_US
dc.proquest.subject0984en_US
dc.proquestyesYesen_US
dc.publisherLethbridge, Alta. : University of Lethbridge, Dept. of Mathematics and Computer Sciencesen_US
dc.publisher.departmentDepartment of Mathematics and Computer Scienceen_US
dc.publisher.facultyArts and Scienceen_US
dc.relation.ispartofseriesThesis (University of Lethbridge. Faculty of Arts and Science)en_US
dc.subjectReversible computingen_US
dc.subjectDissertations, Academic
dc.titleSynthesis, testing and tolerance in reversible logicen_US
dc.typeThesisen_US
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