A reconfigurable and scalable efficient architecture for AES
| dc.contributor.author | Li, Ke | |
| dc.contributor.author | University of Lethbridge. Faculty of Arts and Science | |
| dc.contributor.supervisor | Li, Hua | |
| dc.date.accessioned | 2009-10-13T15:44:59Z | |
| dc.date.available | 2009-10-13T15:44:59Z | |
| dc.date.issued | 2008 | |
| dc.degree.level | Masters | |
| dc.description | ix, 77 leaves : ill. ; 29 cm. | en |
| dc.description.abstract | A new 32-bit reconfigurable FPGA implementation of AES algorithm is presented in this thesis. It employs a single round architecture to minimize the hardware cost. The combinational logic implementation of S-Box ensures the suitability for non-Block RAMs (BRAMs) FPGA devices. Fully composite field GF((24)2) based encryption and keyschedule lead to the lower hardware complexity and convenience for the efficient subpipelining. For the first time, a subpipelined on-the-fly keyschedule over composite field GF((24)2) is applied for the all standard key sizes (128-, 192-, 256-bit). The proposed architecture achieves a throughput of 805.82Mbits/s using 523 slices with a ratio throughput/slice of 1.54Mbps/Slice on Xilinx Virtex2 XC2V2000 ff896 device. | en |
| dc.identifier.uri | https://hdl.handle.net/10133/778 | |
| dc.language.iso | en_US | en |
| dc.publisher | Lethbridge, Alta. : University of Lethbridge, Deptartment of Mathematics and Computer Science, 2008 | en |
| dc.publisher.department | Mathematics and Computer Science | en |
| dc.publisher.faculty | Arts and Science | en |
| dc.relation.ispartofseries | Thesis (University of Lethbridge. Faculty of Arts and Science) | en |
| dc.subject | Data encryption (Computer science) | en |
| dc.subject | Dissertations, Academic | en |
| dc.title | A reconfigurable and scalable efficient architecture for AES | en |
| dc.type | Thesis | en |