Reconfigurable and compact modular polynomial multiplier in Galois field for the security of IoT

Abstract

The rise of the Internet of Things (IoT) has intensified the need for secure, low-power cryptographic hardware capable of operating efficiently in constrained environments. This thesis presents the design and implementation of reconfigurable and compact modular polynomial multipliers over Galois Fields (GF), specifically tailored for the security demands of IoT devices. Leveraging polynomial basis arithmetic in GF(2m), the proposed designs emphasize hardware efficiency, adaptability, and cryptographic robustness for Elliptic Curve Cryptography (ECC) applications. The proposed multipliers were synthesized and validated on multiple FPGA platforms including Spartan-7, Zynq UltraScale+, and Artix-7 using the AMD Xilinx Vivado toolchain. The Karatsuba reconfigurable multiplier achieved the best area-delay product (ADP) across platforms. Analytical and experimental comparisons confirm that the reconfigurable approaches significantly outperform conventional designs in terms of efficiency and scalability. This research provides a practical and versatile foundation for cryptographic accelerators in future low-power and high-security IoT systems.