Minimization of lines in reversible circuits
dc.contributor.author | Law, Jayati J. | |
dc.contributor.author | University of Lethbridge. Faculty of Arts and Science | |
dc.contributor.supervisor | Rice, Jacqueline E. | |
dc.date.accessioned | 2015-08-27T21:45:54Z | |
dc.date.available | 2015-08-27T21:45:54Z | |
dc.date.issued | 2015 | |
dc.degree.level | Masters | en_US |
dc.description.abstract | Reversible computing has been theoretically shown to be an efficient approach over conventional computing due to the property of virtually zero power dissipation. A major concern in reversible circuits is the number of circuit lines or qubits which are a limited resource. In this thesis we explore the line reduction problem using a decision diagram based synthesis approach and introduce a line reduction algorithm— Minimization of lines using Ordered Kronecker Functional Decision Diagrams (MOKFDD). The algorithm uses a new sub-circuit for a positive Davio node structure in addition to the existing node structures. We also present a shared node ordering for OKFDDs. OKFDDs are a combination of OBDDs and OFDDs. The experimental results shows that the number of circuit lines and quantum cost can be reduced with our proposed approach. | en_US |
dc.description.sponsorship | NSERC | en_US |
dc.embargo | No | en_US |
dc.identifier.uri | https://hdl.handle.net/10133/3729 | |
dc.language.iso | en_CA | en_US |
dc.proquest.subject | 0984 | en_US |
dc.proquest.subject | 0544 | en_US |
dc.proquestyes | Yes | en_US |
dc.publisher | Lethbridge, Alta. : University of Lethbridge, Dept. of Mathematics and Computer Science | en_US |
dc.publisher.department | Department of Mathematics and Computer Science | en_US |
dc.publisher.faculty | Arts and Science | en_US |
dc.relation.ispartofseries | Thesis (University of Lethbridge. Faculty of Arts and Science) | en_US |
dc.subject | Ordered Kronecker Functional Decision Diagrams | en_US |
dc.subject | OKFDDs | en_US |
dc.subject | reversible logic | en_US |
dc.subject | Boolean function | en_US |
dc.subject | logic synthesis | en_US |
dc.subject | line reduction | en_US |
dc.title | Minimization of lines in reversible circuits | en_US |
dc.type | Thesis | en_US |